1. Field of the Invention
The present invention relates to semiconductor integrated circuits, and more particularly, to sense amplifiers and differential amplifiers.
2. Description of the Related Art
There are two types of sense amplifiers commonly used for amplifying signals in semiconductor integrated circuits, current sense amplifiers and voltage sense-amplifiers. Current sense amplifiers are widely used since they can operate faster than voltage sense amplifiers. FIG. 1 shows a conventional sense amplifier circuit that includes a current sense amplifier 10, a full differential amplifier 12, and a latch 14. When an enable signal EN is at a high level, NMOS transistors MN11, MN5, and MN8 are on and provide current paths to enable operation of the current amplifier 10, the full differential amplifier 12, and the latch 14, respectively. During a sensing time when the enable signal EN is at a high level, the voltage swings of the output signals SAOUT and SAOUTB of the current sense amplifier 10 are small. Accordingly, the amplification speed of the current sense amplifier 10 cannot directly convert the output signals SAOUT and SAOUTB to a CMOS voltage level. To increase the amplification speed, the full differential amplifier 12 further amplifies the output signal of the current sense amplifier 10 and outputs the amplified signals OUT and OUTB to the latch 14. The latch 14 latches the output signals OUT and OUTB from the full differential amplifier 12 and provides latched output signals DOUT and DOUTB.
In differential amplifier 12, a first NMOS transistor MN1, a second NMOS transistor MN2, a first PMOS transistor MP1, and a second PMOS transistor MP2 operate as a first differential amplifying unit that generates the output signal OUT. When the voltage of an input signal SAOUT input through node 16 functioning as an input port becomes higher than the voltage of a complementary input signal SAOUTB input through node 18 functioning as a complementary input port, the voltage of the output signal OUT at an output port 24 increases. A third NMOS transistor MN3, a fourth NMOS transistor MN4, a third PMOS transistor MP3, and a fourth PMOS transistor MP4 operate as a second differential amplifying unit that generates the complementary output signal OUTB. Accordingly, the voltage of the complementary output signal OUTB at a complementary output port 26 decreases when the voltage of the input signal SAOUT becomes higher than that of the complementary input signal SAOUTB.
When the voltage of the input signal SAOUT becomes lower than the voltage of the complementary input signal SAOUTB, the first differential amplifying unit decreases the voltage of the output signal OUT, and the second differential amplifying unit increases the voltage of the complementary output signal OUTB. The voltage difference between the output signal OUT and the complementary output signal OUTB is proportionate to the voltage difference between the input signal IN and the complementary input signal INB.
The output signal OUT and the complementary output signal OUTB are the input signals of the latch 14. The latch 14 includes a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, an eighth NMOS transistor MN8, a fifth PMOS transistor MP5, and a sixth PMOS transistor MP6. The latch 14 performs an effective latch operation when the voltage levels of the output signal OUT and the complementary output signal OUTB from the full differential amplifier 12 near the turn-on voltage of the NMOS transistors MN6 and MN7, respectively. If either the output signal OUT or the complementary output signal OUTB is higher than the turn-on voltage of the corresponding NMOS transistor MN6 or MN7, the latch 14 performs the latch operation when the other signal OUTB or OUT is lower than the turn-off voltage of the corresponding NMOS transistor MN7 or MN6. In FIG. 1, the latch circuit 14 outputs the output signal DOUT and the complementary output signal DOUTB.
In general, transistors in the sense amplifier of FIG. 1 are sized so that when a supply voltage VDD is low, the mean value of the output signal OUT and the complementary output signal OUTB is around the turn-on voltage of the NMOS transistors MN6 and MN7. However, the channel length modulation effect of the PMOS transistors (e.g., transistors MP1, MP2, MP3, and MP4) becomes larger than the channel length modulation effect of the NMOS transistors (e.g., MN1, MN2, MN3, and MN4) as the supply voltage VDD increases. Accordingly, when the supply voltage VDD increases, the mean voltage of the output signal OUT and the complementary output signal OUTB increases. Accordingly, the NMOS transistors MN6 and MN7 in the latch 14 do not operate effectively. More specifically, the output signal OUT, which is applied to the gate of the sixth NMOS transistor MN6, and the complementary output signal OUTB, which is applied to the gate of the seventh NMOS transistor MN7, strongly turn on transistors MN6 and MN7. This can cause errors in the latch operation. Accordingly, the latch circuit 14 can malfunction when the semiconductor integrated circuit is tested in a high voltage test enable (HITE) mode, where the supply voltage is a high voltage. Therefore, normal testing of the semiconductor integrated circuit in the HITE mode is not possible.
To solve the above problem, the design of the full differential amplifier 12 can make the second PMOS transistor MP2 and the third PMOS transistor MP3 smaller. In this case, the gain of the full differential amplifier is reduced.
The current sense amplifier 10 shown in FIG. 1 is widely used since the current sense amplifier 10 operates faster than a voltage sense amplifier. However, the operation of the current sense amplifier 10 becomes unstable since a positive feedback circuit is used to effectively receive a current input signal. For the current sense amplifier 10, reference numerals Il and I2 denote current signals input through the input ports 15 and 17, respectively. Signals SAOUT and SAOUTB are output through node 16 functioning as an output port and node 18 functioning as a complementary output port, respectively.
To explain the operation of the current sense amplifier 10, the transconductance of the ninth NMOS transistor MN9 and the tenth NMOS transistor MN10 is referred to herein as gmn. The transconductance of the seventh PMOS transistor MP7 and the eighth PMOS transistor MP8 is referred to as gmp. xcex94I is the difference between the input current I1 and the complementary input current I2 (xcex94I=I1xe2x88x92I2). The voltage difference between the output voltage SAOUT and the complementary output voltage SAOUTB is about equal to xcex94I/gmn. The difference between the current value amplified by the seventh PMOS transistor MP7 and the current value amplified by the eighth PMOS transistor MP8 is xcex94Ixc3x97gmp/gmn. Since this value must be equal to xcex94I, which is the difference between the input current signals I1 and I2, the transconductance gmp of the PMOS transistors MP7 and MP8 must be equal to the transconductance gmn of the NMOS transistors MN9 and MN10.
When the sizes of the seventh PMOS transistor MP7 and the eighth PMOS transistor MP8 are increased to increase the gains of the seventh PMOS transistor MP7 and the eighth PMOS transistor MP8, transconductance gmp becomes larger than transconductance gmn. Accordingly, the seventh PMOS transistor MP7 and the eighth PMOS transistor MP8 amplify the input current signals with a current difference larger than xcex94I, which is the difference between the input current signals. Therefore, the values associated with the input current signals I1 and I2 can be exchanged, and the current sense amplifier 10 goes to an unstable state. The transconductance gmp must be less than or equal to transconductance gmn for stability. However, as transconductance gmp becomes smaller than transconductance gmn, the operation speed is reduced since the efficiency of the current sense amplifier sensing the current deteriorates. Therefore, the values of transconductances gmn and gmp must be determined considering a trade-off between stability and speed.
In general, since the channel length modulation effect of the PMOS transistor is larger than the channel length modulation effect of the NMOS transistor, the transconductance of the PMOS transistor is larger than the transconductance of the NMOS transistor.
FIG. 2 shows an NMOS diode and a PMOS diode for illustrating the transconductances of an NMOS transistor and a PMOS transistor, respectively. The transistors have gates and drains connected to form diodes. The current-voltage characteristic curves of the transistor diodes shown in FIG. 2 are shown in FIG. 3. The slopes of the current-voltage characteristic curves indicate the transconductances at different voltages.
As shown in FIG. 3, at gate-source voltages Vgsn and Vsgp larger than a voltage Vc, the slope of the current-voltage characteristic curve of the PMOS transistor is larger than the slope of the current-voltage characteristic curve of the NMOS transistor. The transconductance gmp becomes larger than the transconductance gmn as the applied voltage increases. In the conventional current sense amplifier, when the transconductance gmp of a PMOS transistor is equal to the transconductance gmn of an NMOS transistor at a low voltage, the transconductance gmp of the PMOS transistor becomes larger than the transconductance gmn of the NMOS transistor as the supply voltage increases. Therefore, the operation of the current sense amplifier becomes unstable.
In accordance with an aspect of the present invention, a sense amplifier of a semiconductor integrated circuit includes a full differential amplifier capable of stabilizing the operation of a latch circuit and easily controlling voltage gain by reducing the mean voltage level of an output signal even when a supply voltage increases.
Another aspect of the present invention provides a current sense amplifier that stably operates at high speed.
In one embodiment of the invention, a semiconductor integrated circuit includes a sense amplifier that receives and amplifies complementary input signals, a full differential amplifier that amplifies the output of the sense amplifier, and a latch that latches the output of the full differential amplifier. The full differential amplifier includes a first differential amplifying unit, a second differential amplifying unit, and an output voltage level control circuit. The first differential amplifying unit increases the voltage of a first output port when the level of an input signal input through a first input port becomes higher than the level of a complementary input signal input through a first complementary input port and decreases the voltage of the first output port when the level of the input signal becomes lower than the level of the complementary input signal. The second differential amplifying unit decreases the voltage of a first complementary output port when the level of the input signal becomes higher than the level of the complementary input signal and increases the voltage of the first complementary output port when the level of the input signal becomes lower than the level of the first complementary input signal. The output voltage level control circuit is connected between the first output port and the first complementary output port and controls the voltage levels of the signals output from the first output port and the first complementary output port.
The output voltage level control circuit preferably includes an output voltage mean value sensing unit and an output voltage mean value controller. The output voltage mean value sensing unit senses the mean value of the voltage levels of the signals output from the first output port and the first complementary output port, and the output voltage mean value controller prevents the mean value of the output voltage levels from increasing beyond a predetermined limit. The output voltage mean value sensing unit preferably includes a first resistor and a second resistor serially connected between the first output port and the first complementary output port, and the mean value of the output voltage levels is output from a node between the first resistor and the second resistor. The resistance of the first resistor is preferably equal to the resistance of the second resistor. One embodiment of the output voltage mean value controller includes an NMOS transistor, wherein the gate and the drain of the NMOS transistor are connected to the node between the first resistor and the second resistor, and the source of the NMOS transistor is grounded.
Another embodiment of the output voltage mean value controller preferably includes a first NMOS transistor and a second NMOS transistor. The gate of the first NMOS transistor and the gate of the second NMOS transistor are connected to the node between the first resistor and the second resistor. The drain of the first NMOS transistor is connected to the first output port, and the drain of the second NMOS transistor is connected to the first complementary output port. The sources of the first NMOS transistor and the second NMOS transistor are grounded.
Preferably, the full differential amplifier further includes an operation controller connected to the first differential amplifying unit, the second differential amplifying unit, and the output voltage level control circuit. The operation controller controls the operation of the first differential amplifying unit, the second differential amplifying unit, and the output voltage level control circuit according to an enable signal.
In an exemplary embodiment, the first differential amplifying unit includes first and second PMOS transistors and first and second NMOS transistors. A supply voltage is applied to the sources of the first and second PMOS transistors. The drain and the gate of the first PMOS transistor are connected. The gate of the second PMOS transistor is connected to the gate of the first PMOS transistor, and the drain of the second PMOS transistor is connected to the first output port. The gate of the first NMOS transistor is connected to the first input port, and the drain of the first NMOS transistor is connected to the drain of the first PMOS transistor. The gate of the second NMOS transistor is connected to the first complementary input port, and the drain of the second NMOS transistor is connected to the first output port. The second differential amplifying unit includes third and fourth PMOS transistors and third and fourth NMOS transistors. The supply voltage is applied to the sources of the third and fourth PMOS transistors. The drain of the third PMOS transistor is connected to the first complementary output port. The drain and the gate of the fourth PMOS transistor are connected to the gate of the third PMOS transistor. The gate of the third NMOS transistor is connected to the first input port, and the drain of the third NMOS transistor is connected to the first complementary output. The drain of the fourth NMOS transistor is connected to the drain of the fourth PMOS transistor, and the gate of the fourth NMOS transistor is connected to the first complementary input port. The operation controller includes a fifth NMOS transistor wherein the drain of the fifth NMOS transistor is connected to the sources of the first, second, third, and fourth NMOS transistors and the output voltage mean value controller.
The sense amplifier includes: a second input port; a second complementary input port; first, second, third, and fourth transistors; and first and second resistors. The second input port receives a first current signal, and the second complementary input port receives a second current signal. The first and second transistors, which are cross coupled to each other, receive current signals from the second input port and the second complementary input port, respectively, and output a first output signal and a second output signal, respectively, to a second output port and a second complementary output port, respectively. The third and fourth transistors supply current to the second output port and the second complementary output port, respectively. The first resistor is between the second input port and the first transistor, and a second resistor is between the second complementary input port and the second transistor. The first resistor and the second resistor are preferably as close as possible to the first transistor and the second transistor, respectively.
Preferably, the sense amplifier further includes a fifth transistor that forms a current path so that the third transistor and the fourth transistor operate in response to an enable signal. The third transistor and the fourth transistor of the sense amplifier are preferably connected to each other to form diodes. The first transistor and the second transistor are preferably PMOS transistors, and the third transistor, the fourth transistor, and the fifth transistor are preferably NMOS transistors.
The first resistor can be directly formed in the first transistor by forming one contact to the source electrode of the first transistor and forming multiple contacts to the drain electrode of the first transistor, so that the contact resistance of the source electrode of the first transistor provides the resistance associated with the first resistor. Similarly, the second resistor can be directly formed in the second transistor by forming one contact to the source electrode of the second transistor and forming multiple contacts to the drain electrode of the second transistor, so that the contact resistance of the source electrode of the second transistor provides the resistance of the second resistor.
Alternatively, the first resistor is directly formed in the first transistor by having the contact of the source electrode of the first transistor separated from the gate electrode of the first transistor so that the resistance of the source electrode provides the resistance of the first resistor. Similarly, the second resistor can be directly formed in the second transistor by having the contact of the source electrode of the second transistor separated from the gate electrode of the second transistor so that the resistance of the source electrode provides the resistance of the second resistor.
In another alternative, the first resistor can be directly formed in the first transistor by forming a shallow active region for the source electrode of the first transistor so that the active resistance of the source electrode is equal to the resistance of the first resistor. The second resistor is directly formed in the second transistor by forming a shallow active region for the source electrode of the second transistor so that the active resistance of the source is equal to the resistance of the second resistor.
In yet another alternative, the first resistor can be directly formed in the first transistor having a low dopant density for the source of the first transistor so that the active resistance associated with the source of the first transistor provides the resistance of the first resistor. Similarly, the second resistor can be directly formed in the second transistor having a low dopant density for the source of the second transistor so that the active resistance associated with the source of the second transistor provides the resistance of the second resistor.
In accordance with another embodiment of the invention, a full differential amplifier includes a first differential amplifying unit, a second differential amplifying unit, and an output voltage level control circuit. The first differential amplifying unit increases the voltage of a first output port when the level of an input signal input through a first input port becomes higher than the level of a complementary input signal input through a first complementary input port and reduces the voltage of the first output port when the level of the input signal becomes lower than the level of the complementary input signal. The second differential amplifying unit reduces the voltage of a first complementary output port when the level of the input signal becomes higher than the level of the complementary input signal and increases the voltage of the first complementary output port when the level of the input signal becomes lower than the level of the first complementary input signal. The output voltage level control circuit, which is between the first output port and the first complementary output port, controls the mean voltage level of the output signals from the first output port and the first complementary output port.
In accordance with another embodiment of the invention, a current sense amplifier includes a first input port for receiving a first current signal and a first complementary input port for receiving a second current signal. A first transistor and a second transistor, which are cross coupled to each other, receive the current signals from the first input port and the first complementary input port and output a first output signal and a second output signal to a first output port and a first complementary output port. A third transistor and a fourth transistor supply current to the first output port and the first complementary output port. The current sense amplifier further includes a first resistor serially connected between the first input port and the first transistor and a second resistor serially connected between the first complementary input port and the second transistor.